vexriscv

FPGA-friendly implementation of the RISC-V ISA CPU, designed to be highly configurable and efficient. It supports the RV32IM instruction set and features a five-stage pipeline: Fetch, Decode, Execute, Memory, and WriteBack, achieving a performance of 1.44 DMIPS/MHz when fully enabled. VexRiscv is particularly useful for developers and engineers working on FPGA-based projects requiring a customizable and high-performance CPU core.