yosys

Open-source software framework designed for Verilog RTL synthesis, converting Verilog code into a gate-level netlist. Yosys provides functionalities for simulation, formal verification, and FPGA programming, distinguishing itself with its extensibility and support for various synthesis flows. It is primarily used by hardware designers and engineers involved in digital circuit design and verification.

yosys was discovered on June 25th 2020 and it currently has a search volume of 2.4K with a growth of +335%.